Principal Physical Verification Engineer
Company: Chelsea Search Group
Location: San Jose
Posted on: April 1, 2026
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Job Description:
Principal Physical Verification Engineer About the Role: We are
seeking a Principal Physical Verification Engineering to be part of
the Physical Design team delivering complex digital blocks and
full-chip implementations in advanced process nodes. This role owns
execution of all aspects of Physical Verification on advanced TSMC
nodes. Candidates have completed multiple successful tapeouts.
Candidates be able to drive methodology, quality, and predictable
delivery across multiple programs. You will partner closely with
analog design team and PD team to ensure designs meet aggressive
manufacturability, and schedule goals. Key Responsibilities: Team &
Project Leadership • Lead full chip Physical Verification effort •
Own execution plans, schedules for full-chip • Drive accountability
for quality, milestones, and tapeout readiness. • Conduct full chip
and blocks PV checks Physical Verification Ownership • Ownership of
full chip verification • Work with internal analog team to ensure
clean IP delivery • Responsible for running and analyzing
DRC/ERC/LUP/PERC results • Experience with using either ICV or
Calibre verification tools • Understanding advance TSMC DRC rules
Cross-Functional Collaboration • Partner with analog, block, chip
top owners to ensure clean floorplan • Provide early guidance on
corner case requirements • Influence floorplan constraints,
hierarchy, and implementation strategy. • Participate in tapeout
readiness reviews. Required Qualifications: • Bachelor’s or
Master’s degree in Electrical Engineering or related field. • 5
years of experience with full chip verifications Proven hands-on
experience with: • Physical Verification tool (ICV/Calibre) • Able
to assemble a flow to support block/chip level PV Strong expertise
in: • Floorplanning to avoid DRC/LVS issues • Provide guidance to
analog IP team to allow for clean integration Preferred
Qualifications: • Experience in advanced technology nodes (7nm,
5nm, 3nm). • Automation skills using Tcl, Python, or shell
scripting. Javier Leon Talent Acquisition Chelsea Search Group
619-227-3193 cell FJLrecruiter@gmail.com
www.LinkedIn.com/in/JavierLeon (are we connected?)
Keywords: Chelsea Search Group, Davis , Principal Physical Verification Engineer, Engineering , San Jose, California
